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1 ltc1421/ltc1421-2.5 hot swap controller features n allows safe board insertion and removal from a live backplane n system reset and power good control outputs n programmable electronic circuit breaker n user programmable supply voltage power-up rate n high side driver for two external n-channels n controls supply voltages from 3v to 12v n connection inputs detect board insertion or removal n undervoltage lockout n power-on reset input descriptio n u n hot board insertion n electronic circuit breaker applicatio n s u the ltc ? 1421/ltc1421-2.5 are hot swap tm controllers that allow a board to be safely inserted and removed from a live backplane. using external n-channel pass transistors, the board supply voltages can be ramped up at a program- mable rate. two high side switch drivers control the n- channel gates for supply voltages ranging from 3v to 12v. a programmable electronic circuit breaker protects against shorts. warning signals indicate that the circuit breaker has tripped, a power failure has occurred or that the switch drivers are turned off. the reset output can be used to generate a system reset when the power cycles or a fault occurs. the two connect inputs can be used with stag- gered connector pins to indicate board insertion or re- moval. the power-on reset input can be used to cycle the board power or clear the circuit breaker. the trip point of the ground sense comparator is set at 0.1v for ltc1421 and 2.5v for ltc1421-2.5. the ltc1421/ltc1421-2.5 are available in 24-pin so and ssop packages. typical applicatio n u 10 9 14 13 8 11 15 6 7 ramp cpon comp comp + ref fb compout pwrgd reset 2 24 4 3 1 con2 auxv cc fault por con1 v cclo setlo gatelo v outlo ltc1421 gnd disable v cchi sethi gatehi v outhi 16 c2 0.1 m f c1 1 m f r5 16k 5% q1 mtb50n06e r1 0.005 w 17 18 19 20 21 22 5 12 23 r3 1k staggered connector d1 r6 20k 1% c3 220 m f r4 20k 5% r7 7.15k 1% q2 1/2 si4936dy q3 1/2 si4936dy c3 0.47 m f r2 0.025 w + c5 220 m f v ee 12v 1a v dd 12v 1a v cc 5v 5a + c4 220 m f + i/o i/o reset bea beb gnd 1 13 12 m p qs3384 quickswitch quickswitch is a registered trademark of quality semiconductor corporation. 1421 ta01 data bus pc board backplane data bus gnd por fault v cc v dd v ee v cc 1 m f , ltc and lt are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation.
2 ltc1421/ltc1421-2.5 absolute m axi m u m ratings w ww u wu u package / o rder i for atio consult factory for industrial and military grade parts. (note 1) supply voltage (v cclo , v cchi , auxv cc ) .............. 13.2v input voltage (analog pins) ..... C 0.3v to (v cchi + 0.3v) input voltage (digital pins) ................... C 0.3v to 13.2v output voltage (digital pins) .. C 0.3v to (v cclo + 0.3v) output voltage (cpon) ......... C 13.2v to (v cclo + 0.3v) output voltage (v outlo , v outhi ) ........... C 0.3v to 13.2v output voltage (gatelo, gatehi) ........... C 0.3v to 20v operating temperature range .................... 0 c to 70 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c order part number t jmax = 125 c, q ja = 100 c/w (g) t jmax = 125 c, q ja = 85 c/w (sw) 1 2 3 4 5 6 7 8 9 10 11 12 top view sw package 24-lead plastic so g package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 con1 con2 por fault disable pwrgd reset ref cpon ramp fb gnd auxv cc v cclo setlo gatelo v outlo v cchi sethi gatehi v outhi compout comp comp + electrical characteristics v cchi = 12v, v cclo = 5v, t a = 25 c unless otherwise noted (note 2). symbol parameter conditions min typ max units dc characteristics i cclo v cclo supply current con1 = con2 = gnd, por = v cclo l 1.5 3 ma i cchi v cchi supply current con1 = con2 = gnd, por = v cclo l 0.6 1 ma v lko undervoltage lockout v cclo and v cchi 2.28 2.45 2.60 v v lkh undervoltage lockout hysteresis v cclo and v cchi 100 mv v ref reference output voltage no load l 1.220 1.232 1.244 v d v lnr reference line regulation 3v v cclo 12v, no load l 48 mv d v ldr reference load regulation i o = 0ma to C 5ma, sourcing only l 13 mv i rsc reference short-circuit current v ref = 0v C 45 ma v cof comparator offset voltage 0v v cm (v cclo - 1.3v) l 10 mv v cpsr comparator power supply rejection 0v v cm (v cclo - 1.3v), 3v v cclo 12v l 1 mv/v v chst comparator hysteresis 0v v cm (v cclo - 1.3v) 7 mv v rst reset voltage threshold (v outlo ) fb = v outlo l 2.80 2.90 3.00 v fb = floating l 4.50 4.65 4.75 v fb = gnd l 5.75 5.88 6.01 v v rhst reset threshold hysteresis (v outlo ) fb = v outlo 7mv fb = floating 12 mv fb = gnd 15 mv r fb fb pin input resistance 0v v fb v cclo 95 k w v cb circuit breaker trip voltage v cb = (v cclo C v setlo ) or v cb = (v cchi C v sethi ) l 40 50 60 mv v trip output voltage for re-power-up ltc1421 (note 3) 0.1 v ltc1421-2.5 (note 4) 2.5 v ltc1421cg ltc1421csw ltc1421-2.5cg ltc1421-2.5csw
3 ltc1421/ltc1421-2.5 electrical characteristics v cchi = 12v, v cclo = 5v, t a = 25 c unless otherwise noted (note 2). note 3: after power-on reset, the v outlo and v outhi have to drop below the v trip point before the charge pump is restarted. note 4: after power-on reset, the v outlo has to drop below the v trip point before the charge pump is restarted. symbol parameter conditions min typ max units i ramp ramp pin output current charge pump on, v ramp = 0.4v l 11 17 23 m a i cp charge pump output current charge pump on, gatehi = 0v C 600 m a gatelo = 0v C 300 m a d v gatehi gatehi n-channel gate drive v gatehi - v outhi 616v d v gatelo gatelo n-channel gate drive v gatelo - v outlo 10 16 v v auxvcc auxiliary v cc output voltage v cclo = 5v, unloaded 4.5 v v il input low voltage con1, con2, por l 0.8 v v ih input high voltage con1, con2, por l 2v i in input current con1, con2, por = gnd l C30 C60 C90 m a v ol output low voltage reset, compout, pwrgd, disable, fault, l 0.4 v i o = 3ma cpon, i o = 3ma l 1.45 v v oh output high voltage disable, i o = C 3ma l 4v cpon, i o = C 1ma l 3.4 v i pu logic output pull-up current reset, pwrgd, fault = gnd C 15 m a ac characteristics t 1 con1 or con2 to cpon - figure 1, c l = 15pf l 15 20 30 ms t 2 pwrgd - to reset - figure 1, r l = 10k to v cclo , c l = 15pf 160 200 240 ms l 140 200 280 ms t 3 pwrgd - to disable figure 1, c l = 15pf 160 200 240 ms l 140 200 280 ms t 4 por to cpon figure 1, c l = 15pf l 15 20 30 ms t 5 pwrgd to reset figure 1, r l = 10k to v cclo , c l = 15pf 32 m s t 6 por - to cpon - figure 1, c l = 15pf 50 ns t 7 con1 or con2 - to cpon figure 1, c l = 15pf 50 ns t 9 short-circuit detect to fault figure 1, r l = 10k to v cclo , c l = 15pf 20 m s v cclo C setlo = 0mv to 100mv t 10 short-circuit detect to cpon figure 2, c l = 15pf 20 m s v cclo C setlo = 0mv to 100mv t 11 por - to fault - figure 2, r l = 10k to v cclo , c l = 15pf 20 ns t chl comparator high to low comp C = 1.232v, 10mv overdrive l 0.25 0.5 m s r l = 10k to v cclo , c l = 15pf t clh comparator low to high comp C = 1.232v, 10mv overdrive l 1 1.5 m s r l = 10k to v cclo , c l = 15pf the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are reference to ground unless otherwise specified.
4 ltc1421/ltc1421-2.5 typical perfor m a n ce characteristics u w temperature ( c) ?0 1.232 1.234 1.238 25 75 1421 g01 1.230 1.228 ?5 0 50 100 125 1.226 1.224 1.236 reference voltage (v) v cclo = 5v v cchi = 12v reference voltage vs temperature source current (ma) 0 reference voltage (v) 1.235 1.240 1.245 8 1421 g03 1.230 1.225 1.220 2 4 6 10 v cclo = 5v v cchi = 12v reference voltage vs source current gate voltage vs temperature temperature ( c) ?0 21 22 24 25 75 1421 g02 20 19 ?5 0 50 100 125 18 17 23 gate voltage (v) v cclo = 5v v cchi = 12v gatehi gatelo gatelo voltage vs v cclo voltage v cclo voltage (v) 0 20 22 26 610 1421 g04 18 16 24 81214 14 12 24 gatelo voltage (v) v cchi = 12v gatehi voltage vs v cchi voltage v cchi voltage (v) 0 20 22 26 610 1421 g05 18 16 24 81214 14 12 24 gatehi voltage (v) v cclo = 5v i cclo supply current vs temperature temperature ( c) ?0 1400 25 75 1421 g06 1300 ?5 0 50 100 125 1200 1500 i cclo supply current ( m a) v cclo = 5v v cchi = 12v v ol vs i sink cpon voltage vs sink current (charge pump off) i cchi supply current vs temperature temperature ( c) ?0 540 25 75 1421 g07 530 ?5 0 50 100 125 520 550 545 535 525 555 i cchi supply current ( m a) v cclo = 5v v cchi = 12v sink current (ma) 0 0 voltage (mv) 100 200 300 400 500 fault 600 2468 1421 g08 10 v cclo = 5v v cchi = 12v compout pwrgd reset sink current (ma) 0 0 cpon voltage (v) 0.5 1.0 1.5 2.0 2.5 0.5 1.0 1.5 2.0 1421 g09 2.5 3.0 v cclo = 5v v cchi = 12v
5 ltc1421/ltc1421-2.5 typical perfor m a n ce characteristics u w cpon voltage vs source current (charge pump on) source current (ma) 0 0 cpon voltage (v) 1 2 3 4 5 0.5 1.0 1.5 2.0 1421 g10 2.5 3.0 v cclo = 5v v cchi = 12v i cclo supply current vs v cclo voltage v cclo voltage (v) 0 4 5 7 610 1421 g11 3 2 24 81214 1 0 6 i cclo supply current (ma) v cchi = 12v pi n fu n ctio n s uuu con1 (pin 1): ttl level input with a pull-up to v cclo . together with con2, it is used to indicate board connec- tion. the pin must be tied to ground on the host side of the connector. when using staggered connector pins, con1 and con2 must be the shortest and must be placed at opposite corners of the connector. board insertion is assumed after con1 and con2 are both held low for 20ms after power-up. con2 (pin 2): ttl level input with a pull-up to v cclo . together with con1 it is used to indicate board connec- tion. por (pin 3): ttl level input with a pull-up to v cclo . when the pin is pulled low for at least 20ms, a hard reset is generated. both v outlo and v outhi will turn off at a controlled rate. a power-up sequence will not start until the por pin is pulled high. if por is pulled high before v outlo and v outhi are fully discharged, a power-up sequence will not begin until the voltage at v outlo and v outhi are below v trip . the electronic circuit breaker will be reset by pulling por low. fault (pin 4): open drain output to gnd with a weak pull-up to v cclo . the pin is pulled low when an overcur- rent fault is detected at v outlo or v outhi . disable (pin 5): cmos output. the signal is used to disable the boards data bus during insertion or removal. pwrgd (pin 6): open drain output to gnd with a weak pull-up to v cclo . the pin is pulled low immediately after v outlo falls below its reset threshold voltage. the pin is pulled high immediately after v outlo rises above its reset threshold voltage. reset (pin 7): open drain output to gnd with a weak pull-up to v cclo . the pin is pulled low when a reset condition is detected. a reset will be generated when any of the following conditions are met: either con1 or con2 is high, por is pulled low, v cclo or v cchi are below their respective undervoltage lockout thresholds, pwrgd goes low or an overcurrent fault is detected at v outlo or v outhi . reset will go high 200ms after pwrgd goes high. on power failure, reset will go low 32 m s after pwrgd goes low. ref (pin 8): the reference voltage output. v out = 1.232v 1%. the reference can source up to 5ma of current. a 1 m f bypass capacitor is recommended. cpon (pin 9): cmos output that can be pulled below ground. cpon is pulled high when the internal charge pumps for gatelo and gatehi are turned on. cpon is pulled low when the charge pumps are turned off. the pin can be used to control an external mosfet for a C 5v to C 12v supply.
6 ltc1421/ltc1421-2.5 pi n fu n ctio n s uuu ramp (pin 10): analog power-up ramp control pin. by connecting an external capacitor between the ramp and gatehi, a positive linear voltage ramp on gatehi and gatelo is generated on power-up with a slope equal to 20 m a/c ramp. fb (pin 11): analog feedback input. fb is used to set the reset threshold voltage on v cclo . for a 5v supply leave fb floating. for a 3.3v supply, short fb to v cclo . gnd (pin 12): ground comp + (pin 13): noninverting comparator input. comp C (pin 14): inverting comparator input. compout (pin 15): open drain comparator output. v outhi (pin 16): high supply voltage output. this must be the higher of the two supply voltage outputs. gatehi (pin 17): the high side gate drive for the high supply n-channel. an internal charge pump guarantees at least 6v of gate drive. the slope of the voltage rise at gatehi is set by the external capacitor connected between gatehi and ramp. when the circuit breaker trips, gatehi is immediately pulled to gnd. sethi (pin 18): the circuit breaker set pin for the high supply. with a sense resistor placed in the supply path between v cchi and sethi, the circuit breaker will trip when the voltage across the resistor exceeds 50mv for more than 20 m s. to disable the circuit breaker, v cchi and sethi should be shorted together. v cchi (pin 19): the positive supply input. this must be the higher of the two input supply voltages. an undervoltage lockout circuit disables the chip until the voltage at v cchi is greater than 2.45v. v outlo (pin 20): low supply voltage output. this must be the lower of the two supply voltage outputs. gatelo (pin 21): the high side gate drive for the low supply n-channel pass transistor. an internal charge pump guarantees at least 10v of gate drive. the slope of the voltage rise at gatelo is set by the external capacitor connected between gatehi and ramp. when the circuit breaker trips gatelo is immediately pulled to gnd. setlo (pin 22): the circuit breaker set pin for the low supply. with a sense resistor placed in the supply path between v cclo and setlo, the circuit breaker will trip when the voltage across the resistor exceeds 50mv for more than 20 m s. to disable the circuit breaker, v cclo and setlo should be shorted together. v cclo (pin 23): the positive supply input. v cclo must be equal to or lower voltage than v cchi . an undervoltage lockout circuit disables the chip until the voltage at v cclo is greater than 2.45v. auxv cc (pin 24): the supply input for the gatelo and gatehi discharge circuitry. connect a 1 m f capacitor to ground. auxv cc is powered from v cclo via an internal schottky diode and series resistor.
7 ltc1421/ltc1421-2.5 block diagra m w figure 1. nominal operation switching waveforms figure 2. fault detection switching cpon con1 t 1 con2 reset disable por 1421 f01 pwrgd t 2 t 3 t 4 t 6 t 5 t 7 cpon v cclo ?setlo t 9 fault reset por 1421 f02 pwrgd t 2 t 5 t 11 t 6 t 10 switchi g ti e wavefor s uw w + + + + v trip + + 50mv 50mv cpon auxv cc v cchi setlo cp1 cp2 v cclo sethi gatelo ramp gatehi v outhi v outlo 19 22 23 18 21 10 17 16 20 v cc fault con1 con2 por disable 9 24 4 1 2 3 5 20 m a v cc cp3 cp4 cp5 73.5k n1 n2 auxv cc fb ref 11 8 pwrgd 6 reset 7 compout 15 comp 14 comp + 13 1421 bd 71.5k 26.7k 20 m a 20 m a 1.232v reference charge pump undervoltage lockout reset timing v cc v cc v cc + gnd digital control 12
8 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u hot circuit insertion when circuit boards are inserted into a live backplane, the supply bypass capacitors on the board can draw huge transient currents from the backplane power bus as they charge up. the transient currents can cause permanent damage to the connector pins and cause glitches on the system supply, causing other boards in the system to reset. at the same time, the system data bus can be disrupted when the boards data pins make or break connection. the ltc1421 is designed to turn a boards supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. the chip also provides a disable signal for the boards data bus buffer during insertion or removal and provides all the necessary supply supervisory functions for the board. power supply ramping the power supplies on a board are controlled by placing external n-channel pass transistors in the power path (figure 3). r1 and r2 provide current fault detection. by ramping the gate of the pass transistor up at a controlled rate, the transient surge current (i = c ? dv/dt) drawn from the main backplane supply can be limited to a safe value when the board makes connection. figure 3: supply control circuitry 23 110 5v 12v 2 r1 q1 22 21 20 19 18 17 16 + r2 q2 c3 + c4 v cclo setlo gatelo v outlo ltc1421 1421 f03 v cchi sethi gatehi v outhi ramp con1 con2 c ramp v outhi v outlo when power is first applied to the chip, the gates of both n-channels, gatelo and gatehi are pulled low. after the connection sense pins, con1 and con2 are both held low for at least 20ms, a 20 m a reference current is connected from the ramp pin to gnd. the voltage at gatehi begins to rise with a slope equal to 20 m a/c ramp (figure 4), where c ramp is an external capacitor connected between the figure 4. supplies turning on 12v 5v 1421 f4a t 1 t 2 v outhi v outlo slope = 20 m a/c ramp 12v 12v ~1ms 0v 12v 5v cpon 9 b r5 16k 5% b v ee 0v ~1ms 1421 f05 r4 20k 5% c2 0.047 m f c5 220 m f v ee ?2v 1a q3 1/2 mmdf3n0hd ?2v from connector + cpon ltc1421 figure 5. negative supply control ramp and gatehi pins. the voltage at the gatelo pin is clamped one schottky diode drop below gatehi. the ramp time for each supply is equal to: t = (v cc ) (c ramp )/20 m a. during power down the gates are actively pulled down by two internal nfets. a negative supply voltage can be controlled using the cpon pin as shown in figure 5. when the board makes connection, the transistor q3 is turned off because its gate is pulled low to C12v by r4. cpon is also pulled to C12v. when the charge pump is turned on, cpon is pulled to v cclo and the gate of q3 will ramp up with a time constant determined by r4, r5 and c2. when the charge pump is turned off, cpon goes into a high impedance state, the gate of q3 is discharged to v ee with a time constant determined by r4 and c2, and q3 turns off.
9 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u pwrgd and reset the ltc1421 uses a 1.232v bandgap reference, internal resistive divider and a precision voltage comparator to monitor v outlo (figure 6). the reset threshold voltage for v outlo is determined by the fb pin connection as summarized in table 1. when v outlo drops below its reset threshold, the com- parator output goes high, and pwrgd is immediately pulled low (time point 2). after a 32 m s delay, reset is pulled low. the reset delay allows the pwrgd signal to be used as an early warning that a reset is about to occur. if the pwrgd signal is used as a interrupt input to a microprocessor, a short power-down routine can be run before the reset occurs. if v outlo rises above the reset threshold for less than 200ms, the pwrgd output will trip, but the reset output is not affected (time point 3). if v outlo drops below the reset threshold for less than 32 m s, the pwrgd output will trip, but again the reset output will not be affected (time point 5). voltage comparator the uncommitted voltage comparator (comp2) can be used to monitor output voltages other than v outlo . figure 8a shows how the comparator can be used to monitor a 12v supply (v outhi ), while the 5v supply (v outlo ) gener- ates a reset when it dips below 4.65v. when the 12v supply drops below 10.8v, compout will pull low. the fb pin is left floating. figure 8b shows how the comparator can be used to monitor the 5v supply (v outhi ) while the 3.3v supply (v outlo ) generates a reset when it dips below 2.9v. when the 5v supply drops below 4.65v, compout will pull low. the fb pin is tied to v outlo . figure 6. supply monitor block diagram + v cclo v cclo v outlo fb 1421 f06 1.232v 20 m a 20 m a 26.7k pwrgd reset comp1 reset timing ref 73.5k 71.5k v outlo pwrgd reset 64 m s v2 v2 v2 v2 v1 v1 v1 12345 200ms < 200ms 200ms 1421 f07 <64 m s table 1 feedback pin v outlo reset voltage floating 4.65v v outlo 2.90v gnd 5.88v when the v outlo voltage rises above its reset threshold voltage, the comparator output goes low, and pwrgd is immediately pulled high to v cclo by a weak pull-up current source or external resistor (figure 7, time points 1 and 4). after a 200ms delay, reset is pulled high. the weak pull-up current source to v cclo on pwrgd and reset have a series diode so the pins can be pulled above v cclo by an external pull-up resistor without forcing current back into v cclo . figure 7. power monitor waveforms figure 8a. monitor 12v, reset 5v at 4.65v 1421 f08a 10k 5% 107k 1% 13.7k 1% 5v 12v + + v cclo v cclo 1.232v ltc1421 20 m a 20 m a 8 14 13 15 11 16 20 26.7k comp1 comp2 reset timing 73.5k 107k 1% 6 7 71.5k
10 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u a 5k resistor is tied from the fb pin to v outlo , setting the internal threshold to about 2.9v. the new reset threshold voltage is set by the external resistive divider connected to comp2. when v outlo drops below the new threshold, compout pulls fb to ground, changing the internal threshold at comp1 to 5.88v and generating a reset. finally, the comparator may be used to monitor a negative supply as shown in figure 8e. the external resistor divider figure 8c shows how the comparator can be used to generate a reset when the 12v supply (v outhi ) drops below 10.8v. the 5v supply (v outlo ) also generates a reset when it dips below 4.65v. when the 12v supply drops below 10.8v, compout will pull the fb pin low setting the internal threshold voltage for comparator 1 to 5.88v. since v outlo is less than 5.88v, pwrgd immedi- ately goes low and a reset is generated 200ms later. figure 8d shows how the comparator can be used to override the internal reset voltage for a 5v supply on v outlo . + + v cclo v cclo 1421 f08c 1.232v ltc1421 20 m a 20 m a 8 14 13 15 11 16 20 26.7k comp1 comp2 reset timing 73.5k 107k 1% 13.7k 1% 6 7 71.5k 5v 12v figure 8c. reset 12v at 10.8v, reset 5v at 4.65v figure 8e. monitor C 12v at C 10.8v, reset 5v at 4.65v + + v cclo v cclo 1421 f08e 1.232v ltc1421 20 m a 20 m a 8 14 13 15 11 16 20 26.7k comp1 comp2 reset timing 73.5k 107k 1% 10k 5% 13.7k 1% 6 7 71.5k 5v 12v 12v figure 8d. reset 5v at 4.5v + + v cclo v cclo 1421 f08d 1.232v ltc1421 20 m a 20 m a 8 14 13 15 11 16 20 26.7k comp1 comp2 reset timing 73.5k 102k 1% 5k 5% 38.3k 1% 6 7 71.5k 5v 12v + + v cclo v cclo 1421 f08b 1.232v ltc1421 20 m a 20 m a 8 14 13 15 11 16 20 26.7k comp1 comp2 reset timing 73.5k 10k 5% 107k 1% 38.3k 1% 6 7 71.5k 3.3v 5v figure 8b. monitor 5v, reset 3.3v at 2.9v
11 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u is connected between ref (pin 8) and the negative supply and the trip point of comparator 2 set to gnd. soft reset generation a soft reset that doesnt cycle the supply voltage can be generated externally using pin 11 (fb) as shown in figure 9. for a 5v supply the fb pin is left floating to set the internal supply monitor trip voltage to 4.65v. however, if the fb pin is pulled to ground for more than 64 m s via a push button or open-collector logic gate, the internal trip point will go to 5.88v and the reset pin will pull low. reset will remain low for 200ms after the fb pin is released. the reset signal will also be pulled low when the voltage at the v outlo pin dips below 4.65v for more than 32 m s. when using a 3.3v supply, a 1k resistor must be con- nected from the fb pin to v cclo to set the internal trip point to 2.90v. sense resistor is greater than 50mv for more than 20 m s. when the circuit breaker trips, both n-channel mosfets are quickly turned off, fault and pwrgd go low and reset is pulled low 32 m s later. fault can be connected to a led or a logic signal back to the host to indicate a faulty board. the chip will remain in the tripped state until a power-on reset is generated, or the power on v cchi and v cclo is cycled. if the circuit breaker feature is not used, short v cclo to setlo and v cchi to sethi. if more than 20 m s of response time is needed to reject supply noise, an external resistor and capacitor can be added to the sense circuit as shown in figure 10. figure 9. generating a soft reset undervoltage lockout on power-up, an undervoltage lockout circuit prevents the gatelo and gatehi charge pumps from turning on until v cclo and v cchi have both exceeded 2.45v. electronic circuit breaker the ltc1421 features an electronic circuit breaker func- tion that protects against short circuits or excessive cur- rents on the supplies. by placing a sense resistor between the supply input and set pin of either supply, the circuit breaker will be tripped whenever the voltage across the ltc1421 3.3v 5v 1/6 ls7404 open collector gnd 64 m s 200ms fb 11 7 12 1421 f09 r1 1k r1 used for 3.3v supply only reset reset fb reset logic 23 r sense c f q1 22 r f 21 20 v cclo setlo gatelo v outlo ltc1421 1421 f10 figure 10. short-circuit protection circuit figure 11. auxv cc circuitry gate drive circuitry 10k 1 m f auxv cc 1421 f11 v cclo 24 ltc1421 23 gatelo gatehi 21 17 auxiliary v cc when a short circuit occurs on the board, it is possible to draw enough current to cause the backplane supply voltage to collapse. if the input supply voltage collapses to a low enough voltage and the ltc1421 gate drive circuitry is unable to shut off the n-channel pass transistors, the system might freeze up in a permanent short condition. to prevent this from occurring, the gate discharge cir- cuitry inside the ltc1421 is powered from auxv cc , which is in turn powered from v cclo through an internal schottky diode and current limiting resistor (figure 11).
12 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u when v cclo collapses, there is enough energy stored on the 1 m f capacitor connected to auxv cc to keep the gate discharge circuitry alive long enough to fully turn off the external n-channels. power n-channel selection the r ds(on) of the external pass transistor must be low enough so that the voltage drop across it is about 200mv or less at full current. if the r ds(on) is too high, the voltage drop across the transistor might cause the output voltage to trip the reset circuit. table 2 lists the transistors that are recommended for use with the ltc1421. table 2. n-channel selection guide current part level (a) number manufacturer description 0 to 1 mmdf2n02e motorola dual n-channel so-8 r ds(on) = 0.1 w 1 to 2 mmdf3no2hd motorola dual n-channel so-8 r ds(on) = 0.09 w 2 to 5 mtb30n06 motorola single 30a n-channel dd pak r ds(on) = 0.05 w 5 to 10 mtb50n06e motorola single n-channel dd pak r ds(on) = 0.025 w 10 to 20 mtb75n05hd motorola single n-channel dd pak r ds(on) = 0.0095 w data bus when a board is inserted or removed from the host, care must be given to prevent the system data bus from being corrupted when the data pins make or break contact. one problem is that the fully discharged input or output capaci- tance of the logic gates on the board will draw an inrush current when the data bus pins first make contact. the inrush current can temporarily corrupt the data bus, but usually will not cause long term damage. the problem can be minimized by insuring the input or output data bus capacitance is kept as small as possible. the second, and more serious problem involves the diodes to v cc at the input and output of most logic families (figure 12). v cc out backplane board d1 d2 1421 f12 data bus connector figure 12. typical logic gate loading the data bus figure 13: buffering the data bus + 21 20 c4 2200 m f 22 23 5 12 24 3 14 4 17 7 18 8 21 11 22 12 2 15 5 16 6 system data bus board data bus 19 9 20 10 23 1 13 qs3384 v cc gnd 1421 f13 v cc 5v connector ltc1421 r1 0.005 w q1 mtb50n06e gnd disable with the board initially unpowered, the v cc input to the logic gate is at ground potential. when the data bus pins make contact, the bus line is clamped to ground through the input diode d1 to v cc . large amounts of current can flow through the diode and cause the logic gate to latch up and destroy itself when the power is finally applied. this
13 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u signal is pulled high, turning off the switches. after the board supply voltage ramps up and reset goes high, disable will pull low enabling the switches. board insertion timing when the board is inserted, gnd pin makes contact first, followed by v cchi and v cclo (figure 14, time point 1). disable is immediately pulled high, so the data bus switch is disabled. at the same time con1 and con2 make contact and are shorted to ground on the host side (time point 3). since most boards need to be rocked back and forth to get them in place, there is a period of time when only one side of the connector is making contact. con1 and con2 should be located at opposite ends of the connector. figure 14. board insertion timing can usually be prevented by using logic that does not include the clamping diodes such as the qsi 74fctt family from quality semiconductor, or by using a data bus switch such as the 10-bit qs3384 quickswitch also from quality semiconductor (tel: 408-450-8000). the quickswitch bus switch contains an n-channel placed in series with the data bus. the switch is turned off when the board is inserted and then enabled after the power is stable. the switch inputs and outputs do not have a parasitic diode back to v cc and have very low capacitance. the ltc1421 is designed to work directly with the quickswitch bus switch as shown in figure 13. the disable signal is connected to the enable pins of the qs3384, and each switch is placed in series with a data bus signal. when the board is inserted, the disable v cclo 123 4 5 6 v cchi disable con1 con2 cpon gatehi pwrgd v th1 1421 f14 v outhi v outlo gatelo reset fault por 200ms 20ms
14 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u when con1 and con2 are both forced to ground for more than 20ms, the ltc1421 assumes that the board is fully connected to the host and power-up can begin. when v cclo and v cchi exceed the 2.45v undervoltage lockout threshold, the 20 m a current reference is connected from ramp to gnd, the charge pumps are turned on and cpon is forced high (time point 4). v outhi and v outlo begin to ramp up. when v outlo exceeds the reset threshold volt- age, pwrgd will immediately be forced high (time point 5). after a 200ms delay, reset will be pulled high and disable will be pulled low, enabling the data bus (time point 6). ground sense comparator when por is pulled low for more than 20ms, gatelo and gatehi are pulled to ground and v outlo and v outhi will be discharged. if por is pulled back high while v outlo and v outhi are still ramping down, the discharge will continue. when they drop below the v trip point, a power- up sequence will begin automatically. the trip point poten- tial for ltc1421 is set at 0.1v and 2.5v for ltc1421-2.5. in applications, where either v outlo or v outhi might be forced above 100mv before power-up, the ltc1421-2.5 should be used. this could occur when leakage through the body diode of the logic chips keeps v outlo high or in the case where logic lines are precharged. in other applications, where outputs need to drop to near ground potential before ramping up again to ensure proper initial state for the logic chips, the ltc1421 should be used. power-on reset timing the por input is used to completely cycle the power supplies on the board or to reset the electronic circuit breaker feature. the por pin can be connected to a grounded push button, toggle switch or a logic signal from the host. when por is pulled low for more than 20ms, a power-on reset sequence begins (figure 15, figure 15. power-on reset timing v cchi 123456 7 v cclo disable fault por con1 con2 v outlo v outhi cpon v th2 1421 f15 v th1 20ms 200ms 32 m s gatehi gatelo reset pwrgd
15 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u time point 2). pulses less than 20ms on por are ignored. cpon goes low. both gatehi and gatelo will be actively pulled down to gnd . when v outlo drops below its reset threshold voltage, pwrgd will immediately pull low (time point 3) followed by reset and disable 32 m s later (time point 4). both supplies will be discharged to ground and stay there until por is pulled high. the circuit breaker can be reset by pulling por low. after por is low for more than 20ms, the chip will immediately try to power up the supplies. circuit breaker timing the waveforms for the circuit when a short occurs on either supply during board insertion are shown in figure 16. time points 1 to 4 are the same as the board insertion example, but at time point 5, a short circuit is detected on one of the supplies. the charge pumps are immediately turned off, the outputs v outhi and v outlo are actively pulled to gnd and the cpon and fault pins are pulled low. at time point 6, the circuit breaker is reset by pulling por low. after por has been low for 20ms (time point 7), cpon and fault are pulled high, the 20 m a reference current is connected to ramp and the charge pumps are enabled. v outhi and v outlo ramp up at a controlled rate. when v outlo has exceeded its reset threshold, the pwrgd signal is pulled high (time point 8). after a 200ms delay, reset is pulled high and disable goes low. figure 16. circuit breaker timing v cclo 123 4 5 6 v cchi disable con1 78 9 con2 cpon pwrgd v th1 1421 f16 v outhi gatehi gatelo v outlo reset fault por 20ms 20ms 200ms
16 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u v cclo 1234 v cchi disable con1 con2 cpon pwrgd v th2 1421 f17 v outhi gatehi gatelo v outlo reset fault por 32 m s figure 17. board removal timing board removal timing when the board is removed from the host, the sequence happens in reverse (figure 17). since con1 and con2 are the shortest pins, they break connection first and are internally pulled high (time point 1). the charge pumps are turned off, cpon is pulled low. v outlo and v outhi are actively pulled down. when v outlo falls below its reset threshold (time point 2) pwrgd is pulled low. to allow time for power fail information to be stored in nonvolatile memory, the falling edge of reset (time point 3) is delayed by 32 m s from the falling edged of pwrgd. finally, the input supply pins v cchi and v cclo break contact (time point 4). if staggered pins are not used, the board may be powered down prior to removal by switch- ing the por pin to ground with a toggle switch.
17 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u 5v only applications the ltc1421 may be used in 5v only applications as shown in figure 18. a soft reset can be generated from the backplane via an open-collector inverter driving the fb (pin 11) or by a push button to ground. a hard power reset is generated from the backplane via an open-collector inverter driving the por (pin 3). a hard reset cycles the power on the board or resets the electronic circuit breaker. the comparator is used to monitor the board supply voltage and will pull the powergood signal low as long as the supply remains above 4.65v. note that a soft reset will not affect the powergood signal. the fault signal is also moni- tored to determine that the circuit breaker has tripped. C 48v and 24v applications the ltc1421 may be used in C 48v applications as shown in figure 19. the ltc1421 provides the hot insertion protection, while the 5v supply is generated by a power figure 19. C 48v to 5v hot swappable supply 10 7 14 13 8 2 24 15 1 ltc1421 16 q1 mtb50n06e c1 1 m f c2 1 m f r2 28k 1% 5v 17 18 19 20 21 22 5963 s1 11 12 23 + 1421 f18 5v 5v 5v powergood fault soft reset hard reset r1 0.005 w 1w r3 10.2k 1% reset logic c2 2200 m f 10k 10k 1/6 ls7004 pc board backplane figure 18. 5v only application with soft reset 10 9 13 14 8 11 15 6 7 2 24 4 3 1 16 r4 300 w 1/8w r3 56k 1/2w q2 mpsa06 q1 irfr9110 c1 1 m f 48v 17 18 19 20 21 22 5 12 23 staggered connector + c2 2.2 m f 25v r1 5k 1w d1 5v + c3 2.2 m f 25v + 2 1 5 6 3 c4 100 m f 16v 5v 2a + c4 100 m f 100v + 1421 f19 pc board backplane 48v s1 48v 48v r5 10k 1/2w r6 400 w 1/8w r2 15k 1/8w astrodyne asd 10-48s5 control +in +out in out ltc1421
18 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u figure 23 shows how to use the ltc1421 with a 5v supply and an ltc1430cs8 synchronous step-down switching regulator to generate 3.3v output at up to 10a for micro- processors. resistors r4, r8 and r9 set the turn-on voltage at 4.8v and the turn-off at 4.25v. pushbutton switch s1 provides users a way to reset the output while s2 is used to soft-reset the microprocessor only. figure 24 shows how to use the ltc1421 with a 5v supply and a C 48v supply that is used to generate a 12v supply using a supply module. resistors r3 and r4 are used to monitor the input voltage to the supply module. the module is prevented from turning on via the optoisolator until the input voltage reaches C 36v. zener diode d2 prevents the cpon pin of the ltc1421 from being dam- aged by excessive voltage. figure 25 shows how to use the ltc1421 to do overvolt- age protection. resistors r3 and r4 set the trip point at 7v. when the input supply voltage rises above 7v, q2 is turned on and q1 turned off while q3 helps to discharge the output voltage. figure 26 shows how to use the ltc1421 to control both the power-up and power-down sequence of the outputs. the 5v output would be powered up first followed by the 3v output. at power-down sequence, the 3v output would go down first followed by the 5v supply. figure 27 shows how to use the ltc1421 to switch 3.3v, 5v, 12v and C12v supplies for pci application. the ramp- up rate for 3.3v, 5v and 12v is determined by the ramp capacitor c2 while the C12v supply is controlled by r7 and c3. the internal comparator is being used to do the overcurrent protection for q4 with the trip point set by resistors r6 and r8. the C12v supply does not have overcurrent protection. r10 is used to set the power good signal trip point at 10v. when the 12v output rises above 10v, the pci controller gets a power good signal followed by reset after 200ms. module. the ground pin for the ltc1421 is connected to C 48v; zener diode d1 and resistor r1 provide the positive supply for the chip. bypass capacitor c4 is protected against inrush current by p-channel q1. when the board is inserted into the backplane, transistor q1 is turned off by resistor r2. when the connection sense pins, con1 and con2 have been connected to C 48v for more than 20ms, cpon pulls high turning on q2 and the gate of q1 starts to pull low with a time constant determined by r2, r3 and c3. at the same time, the voltage at the input to the power module starts to ramp up. when the voltage across the inputs to the power module reaches the comparator trip level set by r5 and r6, in this case C 32v, the comparator output pulls high and turns on the 5v supply. a cheaper solution is shown in figure 20 using the lt ? 1170hv switcher. again p-channel transistor q1 pro- tects the bypass capacitors against inrush current and resistors r5 and r6 set the comparator trip voltage. the lt1170hv is turned on via the v c pin. resistors r11, r14 and transistor q4 provide a monitoring path for the reset signal which is level shifted up to 5v through an optoiso- lator. the p-channel power fet is being replaced by an n-channel fet in figure 21 for the C 48v application. again, zener diode d1 and resistor r1 provide the positive supply for the chip. capacitor c1 is to insure q1 stays off when the board is being hot inserted into the backplane. the resistor divider r1 and r2, along with the internal comparator, perform the undervoltage lock out function. q1 would only be turned on when the input supply voltage is lower than C 42v. the power module would then be turned on by the optoisolator, 4n25, when the modules input voltage reaches 47v. figure 22 shows how to use the ltc1421 with a 24v supply and a lt1074ct step-down switcher. resistors r5 and r6 set the turn-on threshold to 22v. all of the supervisory signals can be used without level shifting.
19 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u 10 9 13 14 8 11 15 6 7 2 24 4 3 1 ltc1421 16 r4 300 w 1/8w r3 56k 1/2w q2 mpsa06 q1 irfr9110 c1 1 m f 48v 17 18 19 20 21 22 5 s1 12 23 staggered connector + c2 2.2 m f 25v r1 5k 1w d1 5v + c3 2.2 m f 25v c5 4.7 m f 50v c9 0.33 m f 50v + + c4 4.7 m f 50v 3 5 1 4 + c6 100 m f 100v l1 100 m h d4 mbr3100 q3 2n5401 q4 2n5401 d3 mbr3100 d2 7.5v + 1421 f20 pc board backplane 48v 48v 48v r5 10k 1/2w r6 400 w 1/8w r9 1k 1/8w r8 1k 1/8w r2 15k 1/8w lt1170hvct v cc v c sw gnd fb r10 4.32k 1/8w r11 4.32k 1/8w r13 1.24k 1/8w r14 4.64k 1/8w r12 10k 1/8w v cc 5v 3a reset c7 1000 m f 25v + + c8 1000 m f 25v figure 20. C 48v to 5v hot swappable supply using the lt1170hvct
20 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u figure 21. C 48v to 5v hot swappable supply figure 22. 24v to 5v hot swappable supply using the lt1074ct 10 9 13 14 8 11 15 6 7 2 24 4 3 1 ltc1421 16 r4 300 w 1/8w r3 56k 1/8w q2 mpsa06 q1 irfr9110 c1 1 m f 17 18 19 20 21 22 5 12 23 staggered connector + c2 2.2 m f 25v r1 5k 1/4w d1 5v s1 + c3 2.2 m f 25v + c4 200 m f 50v d4 mbr745 l1 50 m h 2 5 1 3 4 + + c5 500 m f 25v 5v 5a c6 0.01 m f + 1421 f22 pc board backplane 24v por fault r5 10k 1/2w r9 2.7k r6 620 w 1/8w r2 15k 1/8w r7 2.8k 1% r8 2.21k 1% lt1074ct gnd v in v sw v c fb ltc1421 17 8 14 13 15 18 11 1 24 12 3 2 19 22 23 staggered connector 4n25 5v 10a 1421 f21 vicor vi-j30-cy gate in 5k d1 4.3v 0.1 m f 0.1 m f 10k 300 w 100 w 1n4148 4.5k pc board backplane 48v 48v 0.1 m f 100 m f 100 m f ++
21 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u 10 11 6 7 8 14 13 15 9 ltc1421 16 17 18 19 20 21 22 23 1 24 4 5 3 2 12 staggered connector s1 3 5 8 64 1 72 + c1 1 m f 16v c3 220 m f 16v 4 c4 0.1 m f 16v c5 10 m f 16v d1 1n4148 q2 mtd20n03hl q3 mtd20n03hl q4 mtd20n03hl s2 s1: hard power/circuit breaker reset s2: soft reset ltc1430 power-up threshold: 4.8v on 4.25v off 1421 f23 pc board backplane 5v r1 0.005 w 5%,1w c2 0.1 m f 16v ltc1430cs8 v cc pv cc1 comp fb shdn g1 gnd g2 r5 510 w 5% r8 100k 1% r2 0.01 w 5%,1w q1 mtd20n03hl c8 220pf ceramic c7 4700pf ceramic c6 0.1 m f 16v c10 1 m f 16v r9 26.7k 1% r10 10k 5% r6 22 w 5% r7 7.5k 5% r4 10k 1% + + c9 338 m f 10v 6 + 2.7 m h 15a reset 3.3v 10a i max = 15a gnd m p v cc figure 23. 5v to 3.3v hot swappable supply using the ltc1430cs8
22 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u 10 9 13 14 8 11 15 6 2 24 4 3 1 r1 0.005 w 1w q1 mtb50n06e s1 ltc1421 fault irf530 16 c1 1 m f 17 18 19 20 21 22 57 12 23 staggered connector 2 1 5 6 3 c7 100 m f 16v 5v 8a 12v 0.42a 12v 0.42a + 1421 f24 astrodyne asd10-48d12 control +in +out in out c2 1 m f c5 220 m f 100v r3 340 w 1/8w r4 10k 1/8w r5 4.3k 1/8w r6 15k 1/8w c3 0.47 m f r7 1k 1/8w c4 2200 m f 16v + c6 100 m f 16v + + pc board backplane 5v 48v q3 2n5401 figure 24. 5v and C 48v to 12v hot swappable supply 10 7 8 14 13 15 1 24 3 2 12 ltc1421 16 q3 vn2222 c2 0.1 m f c1 1 m f 17 18 19 20 21 22 23 staggered connector + 2200 m f 16v + 100 w 1k 12 w r1 0.005 w 1/2w q1 mtb50n06e q2 vn2222 s1 1421 f25 pc board backplane 5v r4 10k r3 47.5k 5v 8a reset gnd m p v cc figure 25. hot swappable 5v supply with overvoltage protection
23 ltc1421/ltc1421-2.5 applicatio n s i n for m atio n wu u u g package 24-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) dimensions in inches (millimeters) unless otherwise noted. package descriptio n u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s24 (wide) 0996 note 1 0.598 ?0.614* (15.190 ?15.600) 22 21 20 19 18 17 16 15 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 13 14 11 12 23 24 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** g24 ssop 0595 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 0.318 ?0.328* (8.07 ?8.33) 21 22 18 17 16 15 14 13 19 20 23 24 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** sw package 24-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620) figure 26. power-up and power-down sequence controller 10 11 6 7 8 14 13 15 9 1 24 4 5 3 2 12 ltc1421 16 c2 0.1 m f 24v c1 1 m f 16v 0.047 m f 17 18 19 20 21 22 23 staggered connector + c4 2200 m f 16v + c5 0.1 m f 24v + 1k r1 0.005 w 1w r3 1m 5%,1/8w q1 mtb50n06e q2 mtb50n06e s1 1421 f26 pc board backplane 5v 3v r6 200k 5% 1/16w r5 330k 5% 1/16w 3v 8a 5v 8a r2 0.005 w 1w c4 2200 m f 16v + reset gnd m p v cc r4 1k 5% 1/16w
24 ltc1421/ltc1421-2.5 ? linear technology corporation 1996 142125fa lt/tp 1098 2k rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com typical applicatio n u 10 11 6 7 8 14 13 15 9 1 24 4 5 3 2 12 ltc1421 q3 1/2 irf7101 q2 1/2 irf7101 pci connector q1 irf7413 16 17 r11 10 w c2 0.22 m f 24v r4 30 w 18 19 20 21 22 23 q4 irf7413 12v 3.3a circuit breaker 3.3v 11.5a circuit breaker 5v 10a circuit breaker r10 100k r13 5.1k r5 20k r12 10 w c1 1 m f 16v r1 0.005 w 5% 1/2w r14 5.1k r2 0.015 w 5% 1w r8 5.62k 1% 1/16w r3 0.005 w 5% 1w + power good rst # select bits bus enable fault 12v 500ma 3.3v 7.5a 5v 5a on/off data bus ?2v 100ma pci power controller quickswitch r7 130k r9 10 w q5 tp0610t c3 1 m f 24v r6 100 w 1% 1/16w 12v no circuit breaker gnd 1421 f27 all resistors 5%, 1/16w except where noted rst # logic pci peripheral motherboard or backplane figure 27. pci power controller part number description comments ltc1155 dual high side switch driver short-circuit protection and micropower standby operation ltc1477/ltc1478 single and dual protected high side switches inrush current limited, built-in 2a short-circuit protection related parts

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